1. Field of the Disclosure
The disclosure relates generally to microelectromechanical systems (MEMS) and, more particularly, to wafer-level packaging of MEMS devices.
2. Brief Description of Related Technology
Wafer-level encapsulation has become an important packaging method, particularly for microelectromechanical systems (MEMS) and other microsystem or nanoscale devices (collectively referred to herein as “MEMS devices”). MEMS devices are susceptible to damage from contact or exposure to dust, etc. Wafer-level encapsulation provides a convenient means for protecting these devices and thereby enabling them to be handled like conventional IC chips.
With reference to FIGS. 1A and 1B, wafer-level encapsulation is a process in which a device substrate wafer 102 having tens to hundreds of device die is joined to a matching cap wafer (a port of which is shown as element 106), which contains a corresponding number of cavities. After the wafers are joined, each device 104 resides within an “encapsulation region” formed by cap wafer material and the substrate on which the device resides, as shown in FIG. 1. Once sealed, conventional techniques, such as wafer dicing, may be used to separate the individual sealed die from the joined wafers. In many applications, the operational characteristics and behavior of the MEMS device is improved by operation in a low-pressure or high-pressure environment. For these applications, it is vital that the seal between the device wafer and cap wafer is of high-integrity (i.e., exhibits little or no gas leakage).
Silicon-on-insulator (SOI) wafers have been widely used to fabricate a variety of MEMS devices, which are often thereby referred to as “SOI-MEMS” devices. SOI wafers have an active (or working) layer of silicon disposed on a layer of silicon dioxide, which, in turn, is disposed on a silicon handle wafer. To form SOI-MEMS devices, deep reactive-ion-etching (deep-RIE) is used to “cookie-cut” through the active layer to define the device structure, electrodes, and interconnection lines. Multiple electrically-isolated regions within a device die are formed by etching isolation trenches around each region. The isolation trenches extend through the entire thickness of the active layer.
As shown in FIG. 1B, external electrical connection to each electrical (or device) region 108 is often made via wire bond pads 114 which are located outside the bounds of the encapsulation region of the die (as defined by bonding ring 116). This leads to one of two problems: (1) the isolation trenches 110 that define the wire bond pads 114 and interconnect lines 112 pass through the bonding region where the cap wafer material and device substrate are joined, as shown in FIG. 1B, thereby forming leakage paths through which gasses and other fluids can pass; and, (2) electrical interconnect lines must cross the trench region. Therefore, either the hermetic or pressurized environment of the sealed unit is compromised, or it is difficult to form reliable electrical connection to regions within the encapsulation region.